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Joint Test Action Group
<architecture, body, electronics, integrated circuit,
standards, testing> (JTAG, or "IEEE Standard 1149.1") A
standard specifying how to control and monitor the pins of
compliant devices on a printed circuit board.
Each device has four JTAG control lines. There is a common
reset (TRST) and clock (TCLK). The data line daisy chains
one device's TDO pin to the TDI pin on the next device.
The protocol contains commands to read and set the values of
the pins (and, optionally internal registers) of devices.
This is called "boundary scanning". The protocol makes
board testing easier as signals that are not visible at the
board connector may be read and set.
The protocol also allows the testing of equipment, connected
to the JTAG port, to identify components on the board (by
reading the device identification register) and to control and
monitor the device's outputs.
JTAG is not used during normal operation of a board.
JTAG Technologies B.V..
Boundary Scan/JTAG Technical Information - Xilinx, Inc..
Java API for Boundary Scan FAQs - Xilinx Inc..
JTAG Boundary-Scan Test Products - Corelis, Inc..
"Logic analyzers stamping out bugs at the cutting edge", EDN
Access, 1997-04-10.
IEEE 1149.1 Device Architecture - Boundary-Scan Tutorial from
ASSET InterTech, Inc..
"Application-Specific Integrated Circuits", Michael John
Sebatian Smith, published Addison-Wesley - Design Automation
Cafe.
Software Debug options on ASIC cores - Embedded Systems
Programming Archive.
Designing for On-Board Programming Using the IEEE 1149.1
(JTAG) Access Port - Intel.
Built-In Self-Test Using Boundary Scan by Texas Instruments -
EDTN Network.
(1999-11-15)
Try this search on OneLook / Google
Nearby terms:
Joint Bi-level Image Experts Group « Joint Photographic Experts Group « Joint Technical Committee « Joint Test Action Group » jolix » JOLT » Jon Postel
This article was derived from the Free Online Dictionary of Computers and is available under ther terms of the GNU Free Documentation License.
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