cache
<memory management> /kash/ A small fast memory holding
recently accessed data, designed to speed up subsequent access
to the same data. Most often applied to processor-memory
access but also used for a local copy of data accessible over
a network etc.
When data is read from, or written to, main memory a copy is
also saved in the cache, along with the associated main memory
address. The cache monitors addresses of subsequent reads to
see if the required data is already in the cache. If it is (a
cache hit) then it is returned immediately and the main
memory read is aborted (or not started). If the data is not
cached (a cache miss) then it is fetched from main memory
and also saved in the cache.
The cache is built from faster memory chips than main memory
so a cache hit takes much less time to complete than a normal
memory access. The cache may be located on the same
integrated circuit as the CPU, in order to further reduce
the access time. In this case it is often known as primary
cache since there may be a larger, slower secondary cache
outside the CPU chip.
The most important characteristic of a cache is its hit rate
- the fraction of all memory accesses which are satisfied from
the cache. This in turn depends on the cache design but
mostly on its size relative to the main memory. The size is
limited by the cost of fast memory chips.
The hit rate also depends on the access pattern of the
particular program being run (the sequence of addresses being
read and written). Caches rely on two properties of the
access patterns of most programs: temporal locality - if
something is accessed once, it is likely to be accessed again
soon, and spatial locality - if one memory location is
accessed then nearby memory locations are also likely to be
accessed. In order to exploit spatial locality, caches often
operate on several words at a time, a "cache line" or "cache
block". Main memory reads and writes are whole cache lines.
When the processor wants to write to main memory, the data is
first written to the cache on the assumption that the
processor will probably read it again soon. Various different
policies are used. In a write-through cache, data is
written to main memory at the same time as it is cached. In a
write-back cache it is only written to main memory when it
is forced out of the cache.
If all accesses were writes then, with a write-through policy,
every write to the cache would necessitate a main memory
write, thus slowing the system down to main memory speed.
However, statistically, most accesses are reads and most of
these will be satisfied from the cache. Write-through is
simpler than write-back because an entry that is to be
replaced can just be overwritten in the cache as it will
already have been copied to main memory whereas write-back
requires the cache to initiate a main memory write of the
flushed entry followed (for a processor read) by a main memory
read. However, write-back is more efficient because an entry
may be written many times in the cache without a main memory
access.
When the cache is full and it is desired to cache another line
of data then a cache entry is selected to be written back to
main memory or "flushed". The new line is then put in its
place. Which entry is chosen to be flushed is determined by a
"replacement algorithm".
Some processors have separate instruction and data caches.
Both can be active at the same time, allowing an instruction
fetch to overlap with a data read or write. This separation
also avoids the possibility of bad cache conflict between
say the instructions in a loop and some data in an array which
is accessed by that loop.
See also direct mapped cache, fully associative cache,
sector mapping, set associative cache.
(1997-06-25)
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cache block
cache line
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cache coherency
<storage> (Or "cache consistency") /kash koh-heer'n-see/ The
synchronisation of data in multiple caches such that reading
a memory location via any cache will return the most recent
data written to that location via any (other) cache.
Some parallel processors do not cache accesses to shared
memory to avoid the issue of cache coherency. If caches are
used with shared memory then some system is required to detect
when data in one processor's cache should be discarded or
replaced because another processor has updated that memory
location. Several such schemes have been devised.
(1998-11-10)
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cache conflict
<storage> A sequence of accesses to memory repeatedly
overwriting the same cache entry. This can happen if two
blocks of data, which are mapped to the same set of cache
locations, are needed simultaneously.
For example, in the case of a direct mapped cache, if
arrays A, B, and C map to the same range of cache locations,
thrashing will occur when the following loop is executed:
for (i=1; i<n; i++)
C[i] = A[i] + B[i];
Cache conflict can also occur between a program loop and the
data it is accessing.
See also ping-pong.
(1997-01-21)
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cache consistency
cache coherency
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cache hit
<storage> A request to read from memory which can satisfied
from the cache without using the main memory.
Opposite: cache miss.
(1997-01-21)
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cache line
<storage> (Or cache block) The smallest unit of memory than
can be transferred between the main memory and the cache.
Rather than reading a single word or byte from main memory at
a time, each cache entry is usually holds a certain number of
words, known as a "cache line" or "cache block" and a whole
line is read and cached at once. This takes advantage of the
principle of locality of reference: if one location is read
then nearby locations (particularly following locations) are
likely to be read soon afterward. It can also take advantage
of page-mode DRAM which allows faster access to
consecutive locations.
(1997-01-21)
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cache memory
cache
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cache miss
<storage> A request to read from memory which cannot be
satisfied from the cache, for which the main memory has to
be consulted.
Opposite: cache hit.
(1997-01-21)
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Cache On A STick
<architecture> (COAST) Intel Corporation attempt to's
standardise the modular L2 cache subsystem in
Pentium-based computers.
A COAST module should be about 4.35" wide by 1.14" high.
According to earlier specifications from Motorola, a module
between 4.33" and 4.36" wide, and between 1.12" and 1.16" high
is within the COAST standard. Some module vendors, including
some major motherboard suppliers, greatly violate the height
specification.
Another COAST specification violated by many suppliers
concerns clock distribution in synchronous modules. The
specification requires that the clock tree to each synchronous
chip be balanced, i.e. equal length from edge of the connector
to individual chips. An unbalanced clock tree increases
reflections and noise.
For a 256 kilobyte cache module the standard requires the
same clock be used for both chips but some vendors use
separate clocks to reduce loading on the clock driver and
hence increase the clock speed. However, this creates
unbalanced loading in other motherboard configurations, such
as motherboards with soldered caches in the system.
(1996-06-10)
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caching
cache
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This article was derived from the Free Online Dictionary of Computers and is available under ther terms of the GNU Free Documentation License.
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